DESIGN OF A FULL ADDER CIRCUIT

DESIGN OF A FULL ADDER CIRCUIT

ABSTRACT
In this project, two high performance adder cells are proposed. We simulated these two full adder cells using HSPICE in 0.18 µm, CMOS technology and at 25-degree of temperature with supply voltage range from 0.5v to 3.3v with 0.1v steps. Results show that the proposed adders operate successfully when connected to a 0.5 V power supply. The two adders differ in the technology applied to their gates. While the first circuit applies CMOS technology, the second and optimal one uses Past Transistor Logic. The average power dissipation of the optimum is 4.3269*10-7 watt, which illustrates an amazing performance. This paper demonstrates the PDP and Power Consumption of the proposed adders, and the comparison results among another six full adders.

TABLE OF CONTENTS 
Certification
Dedication
Acknowledgment
Table of content

CHAPTER ONE
1.0       Introduction
1.1       Background of the study
1.2       Aims and objectives
1.3       Significance of the study 
1.4       Limitation

CHAPTER TWO
2.0       Literature review
2.1       Calculation on the design and its layout 
2.2       List and function of components and other materials used
2.3       Relays and its types

CHAPTER THREE
3.0       Wiring diagram
3.1       Circuit diagram
3.2       Specification
3.3       Electrical legend

CHAPTER FOUR

1. 1. Tests carried out
   2. Casing diagram
   3. Problems encountered and solution

CHAPTER FIVE
5.0       Conclusion and Recommendation
5.1       Bill of engineering measurement and evaluation (BEME)
5.2       Appendix
5.3       References                

DESIGN OF A FULL ADDER CIRCUIT